Modern memory devices, such as double data rate (DDR) and graphics double data rate (GDDR) memory devices, typically require a reliable timing control for high-speed operations. At least three types of timing control architectures are currently in use or have been proposed—strobed timing (or “source synchronous timing”), clocked timing, and clock-data-recovery or “clock and data recovery” (CDR). Each of these known approaches has disadvantages which may limit its use in high-performance applications.
In a typical strobed timing architecture, a memory controller (e.g., a graphics processing unit or “GPU”) may be coupled to a DDR or GDDR memory device via a bi-directional data bus, and a pair of strobe paths may run in parallel with the data bus to provide timing control for high-speed data exchange between the memory controller and the memory device. In operation, the memory controller may assert a first strobe signal (or “write strobe”) on one strobe path to provide a timing reference for every transmission of data to the memory device. The memory device may assert a second strobe signal (or “read strobe”) on the other strobe path to provide a timing reference for every transmission of data to the memory controller. With this timing arrangement, the receiving device (i.e., the memory controller during a read operation or the memory device during a write operation) can have a timing reference which is in a controlled phase relationship with the data signal received.
One disadvantage of the traditional strobed timing architecture lies in the requirement of extra wires and related circuitry which are dedicated to the transmission and detection of strobe signals. In addition, the electrical lengths of timing paths (for strobe signals) and data paths (for data signals) must be matched or equalized to avoid skews between the strobe and data signals. This additional requirement tends to increase the complexity of laying out strobe-based memory controllers and memory devices on circuit boards.
Some higher-performance memory devices operate based on a clocked timing architecture and include timing circuitry to generate an internal clock based on a master clock supplied by a memory controller. Write data signals are not sampled according to the timing of write strobe signals but in reference to an internal receive clock signal at the memory. Similarly, read data signals are not sampled according to the timing of read strobe signals but in reference to a receive clock signal at the memory controller.
Compared with the strobed timing architectures, the mismatch between timing paths and data paths is no longer an issue for the clocked timing architecture. However, clocked timing requires proper phase maintenance for the transmit and receive clocks in order to sample data signals correctly at the memory and the memory controller. The phase maintenance circuitry may be costly to design and consumes additional chip power. The phase maintenance requirement may be difficult to satisfy when environmental drift components are present in the memory device to cause continual phase drifts in its local clock. Furthermore, tracking of the phase drifts may be too slow to satisfy high-performance needs of modern data memory devices.
In a typical clock-data-recovery (CDR) architecture, a receiver may receive a data stream without an accompanying clock signal or any other timing signals. The receiver may generate a clock from an approximate frequency reference and then phase-align to the transitions in the data stream with a phase-locked loop (PLL). This clock recovery scheme is effective only when the data stream has a sufficiently high transition frequency. To ensure frequent transitions, some encoding scheme may be implemented on the data stream, such as the well-known 8B/10B encoding method which maps 8-bit data to a 10-bit symbol.
While it does not involve any dedicated signaling path or any clock phase maintenance, the CDR architecture still requires dedicated clock phase extraction circuitry (e.g., PLL). The 8B/10B encoding not only leads to overhead costs, but also reduces useful bandwidth.
In view of the foregoing, it would be desirable to provide a technique for improved timing control of electronic devices which overcomes the above-described inadequacies and shortcomings.